82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 27

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

switched to another one’ - are: (The T0 selected input clock is disquali-
fied AND Another input clock is switched to) OR (In Revertive switch, a
qualified input clock with a higher priority is switched to) OR (The T0
selected input clock is switched to another one by External Fast selec-
tion or Forced selection).
Functional Description
IDT82V3352
Notes to
The causes of Item 4, 9, 12, 15 - ‘the T0 selected input clock is
1. Reset.
2. An input clock is selected.
3. The T0 selected input clock is disqualified AND No qualified input clock is available.
4. The T0 selected input clock is switched to another one.
5. The T0 selected input clock is locked (the T0_DPLL_LOCK bit is ‘1’).
6. The T0 selected input clock is disqualified AND No qualified input clock is available.
7. The T0 selected input clock is unlocked (the T0_DPLL_LOCK bit is ‘0’).
8. The T0 selected input clock is locked again (the T0_DPLL_LOCK bit is ‘1’).
9. The T0 selected input clock is switched to another one.
10. The T0 selected input clock is locked (the T0_DPLL_LOCK bit is ‘1’).
11. The T0 selected input clock is disqualified AND No qualified input clock is available.
12. The T0 selected input clock is switched to another one.
13. The T0 selected input clock is disqualified AND No qualified input clock is available.
14. An input clock is selected.
15. The T0 selected input clock is switched to another one.
Figure
6:
27
path.
Refer to
Table 13
for details about the input clock qualification for T0
SYNCHRONOUS ETHERNET WAN PLL
March 23, 2009