82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 21

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

Table 9: Related Bit / Register in Chapter 3.6
3.6.2
T0_INPUT_SEL[3:0] bits. The results of input clocks quality monitoring
(refer to
input clock selection.
3.6.3
validity and priority. The validity depends on the results of input clock
quality monitoring (refer to
In all the qualified input clocks, the one with the highest priority is
selected. The
INn_CMOS_SEL_PRIORITY[3:0] bits (n = 1, 2 or 3) / the
Functional Description
IDT82V3352
In Forced selection, the selected input clock is set by the
In Automatic selection, the input clock selection is determined by its
Chapter 3.5 Input Clock Quality
FORCED SELECTION
AUTOMATIC SELECTION
INn_CMOS_SEL_PRIORITY[3:0] (n = 1, 2 or 3)
INn_DIFF_SEL_PRIORITY[3:0] (n = 1 or 2)
priority is
T0_INPUT_SEL[3:0]
Chapter 3.5 Input Clock Quality
EXT_SW
configured
Bit
Monitoring) do not affect the
by
the corresponding
Monitoring).
21
Table 8: ‘n’ Assigned to the Input Clock
INn_DIFF_SEL_PRIORITY[3:0] bits (n = 1 or 2). If more than one quali-
fied input clock is available and has the same priority, the input clock
with the smallest ‘n’ is selected. See
input
IN1_IN2_CMOS_SEL_PRIORITY_CNFG,
IN1_IN2_DIFF_SEL_PRIORITY_CNFG
IN3_CMOS_SEL_PRIORITY_CNFG
clock.
MON_SW_PBO_CNFG
T0_INPUT_SEL_CNFG
Input Clock
IN1_CMOS
IN2_CMOS
IN3_CMOS
IN1_DIFF
IN2_DIFF
Register
SYNCHRONOUS ETHERNET WAN PLL
Table 8
‘n’ Assigned to the Input Clock
for the ‘n’ assigned to the
1
2
3
4
5
March 23, 2009
Address (Hex)
27 *, 2A *
28 *
0B
50