82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 45

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

Table 30: Register List and Map (Continued)
Programming Information
IDT82V3352
Address
(Hex)
4A
4B
4E
5A
5B
5C
5D
45
47
4F
50
52
53
55
56
57
58
59
IN1_IN2_DIFF_STS - Differential Input
Clock 1 & 2 Status
IN3_CMOS_STS - CMOS Input Clock
3 Status
INPUT_VALID1_STS - Input Clocks
Validity 1
INPUT_VALID2_STS - Input Clocks
Validity 2
PRIORITY_TABLE1_STS - Priority
Status 1 *
PRIORITY_TABLE2_STS - Priority
Status 2 *
T0_INPUT_SEL_CNFG - T0 Selected
Input Clock Configuration
OPERATING_STS - DPLL Operating
Status
T0_OPERATING_MODE_CNFG - T0
DPLL Operating Mode Configuration
T0_DPLL_APLL_PATH_CNFG - T0
DPLL & APLL Path Configuration
T0_DPLL_START_BW_DAMPING_C
NFG - T0 DPLL Start Bandwidth &
Damping Factor Configuration
T0_DPLL_ACQ_BW_DAMPING_CNF
G - T0 DPLL Acquisition Bandwidth &
Damping Factor Configuration
T0_DPLL_LOCKED_BW_DAMPING_
CNFG - T0 DPLL Locked Bandwidth &
Damping Factor Configuration
T0_BW_OVERSHOOT_CNFG - T0
DPLL Bandwidth Overshoot Configu-
ration
PHASE_LOSS_COARSE_LIMIT_CNF
G - Phase Loss Coarse Detector Limit
Configuration *
PHASE_LOSS_FINE_LIMIT_CNFG -
Phase Loss Fine Detector Limit Con-
figuration *
T0_HOLDOVER_MODE_CNFG - T0
DPLL Holdover Mode Configuration
T0_HOLDOVER_FREQ[7:0]_CNFG -
T0 DPLL Holdover Frequency Config-
uration 1
Register Name
PH_LOS_L
AUTO_BW
COARSE_
FINE_PH_
LOS_LIMT
MAN_HOL
EX_SYNC
_ALARM_
T0_DPLL_LOCKED_DAMPING[2:0]
THIRD_HIGHEST_PRIORITY_VALIDATED[3:0]
T0_DPLL_START_DAMPING[2:0]
IMT_EN
DOVER
T0_DPLL_ACQ_DAMPING[2:0]
_SEL
MON
Bit 7
_EN
HIGHEST_PRIORITY_VALIDATED[3:0]
-
-
-
-
-
-
T0 DPLL State Machine Control Registers
T0 DPLL & APLL Configuration Registers
T0 DPLL Input Clock Selection Registers
FAST_LOS
IN2_DIFF_
FREQ_HA
RD_ALAR
WIDE_EN
AUTO_AV
T0_APLL_PATH[3:0]
Bit 6
_SW
M
G
-
-
-
-
-
-
-
SOFT_FRE
FAST_AVG
IN2_DIFF_
NO_ACTIV
MULTI_PH
ITY_ALAR
T0_DPLL_
Q_ALARM
IN2_DIFF
_APP
Bit 5
45
M
-
-
-
-
-
-
T0_HOLDOVER_FREQ[7:0]
IN2_DIFF_
MULTI_PH
PH_LOCK
_8K_4K_2
READ_AV
IN1_DIFF IN2_CMOS IN1_CMOS
_ALARM
K_EN
Bit 4
G
-
-
-
-
-
-
-
SECOND_HIGHEST_PRIORITY_VALIDATED[3:0
T0_ETH_OBSAI_16E1_
T0_DPLL_
TEMP_HOLDOVER_M
T0_LIMT
LOCK
Bit 3
T0_DPLL_LOCKED_BW[4:0]
16T1_SEL[1:0]
T0_DPLL_START_BW[4:0]
-
-
-
-
-
CURRENTLY_SELECTED_INPUT[3:0]
T0_DPLL_ACQ_BW[4:0]
ODE[1:0]
PH_LOS_COARSE_LIMT[3:0]
IN3_CMOS
SYNCHRONOUS ETHERNET WAN PLL
IN1_DIFF_
FREQ_HA
T0_DPLL_OPERATING_MODE[2:0]
RD_ALAR
_FREQ_H
ARD_ALA
T0_INPUT_SEL[3:0]
Bit 2
RM
T0_OPERATING_MODE[2:0]
M
-
-
PH_LOS_FINE_LIMT[2:0]
]
IN3_CMOS
IN1_DIFF_
NO_ACTIV
_NO_ACTI
ITY_ALAR
VITY_ALA
T0_12E1_24T1_E3_T3
Bit 1
RM
M
-
-
-
-
_SEL[1:0]
IN3_CMOS
IN3_CMOS
IN1_DIFF_
PH_LOCK
K_ALARM
_PH_LOC
_ALARM
Bit 0
March 23, 2009
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-
-
Reference
Page
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