82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 56

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

INTERRUPTS1_ENABLE_CNFG - Interrupt Control 1
INTERRUPTS2_ENABLE_CNFG - Interrupt Control 2
Programming Information
IDT82V3352
Address: 11H
Type: Read / Write
Default Value:00XXXXX0
Address: 10H
Type: Read / Write
Default Value: XX0000XX
T0_OPERATING
5 - 1
7 - 6
5 - 4
3 - 2
1 - 0
Bit
Bit
7
6
0
_MODE
7
-
7
T0_OPERATING_MODE
T0_MAIN_REF_FAILED
INn_CMOS
INn_DIFF
Name
IN3_CMOS
T0_MAIN_REF_F
-
-
Name
-
6
-
AILED
6
Reserved.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the input clock validity changes (from
‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’), i.e., when the corresponding INn_DIFF bit (b5/4, 0DH) is ‘1’. Here n is 2 or 1.
0: Disabled. (default)
1: Enabled.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the input clock validity changes (from
‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’), i.e., when the corresponding INn_CMOS bit (b3/2, 0DH) is ‘1’. Here n is 2 or 1.
0: Disabled. (default)
1: Enabled.
Reserved.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the T0 DPLL operating mode
switches, i.e., when the T0_OPERATING_MODE bit (b7, 0EH) is ‘1’.
0: Disabled. (default)
1: Enabled.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the T0 selected input clock
has failed; i.e., when the T0_MAIN_REF_FAILED bit (b6, 0EH) is ‘1’.
0: Disabled. (default)
1: Enabled.
Reserved.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the input clock validity
changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’), i.e., when the corresponding IN3_CMOS bit (b0, 0EH) is ‘1’.
0: Disabled. (default)
1: Enabled.
IN2_DIFF
5
5
-
IN1_DIFF
4
4
-
56
IN2_CMOS
3
3
-
Description
Description
IN1_CMOS
2
2
-
SYNCHRONOUS ETHERNET WAN PLL
1
1
-
-
March 23, 2009
IN3_CMOS
0
0
-