82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 94

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

DPLL_FREQ_SOFT_LIMIT_CNFG - DPLL Soft Limit Configuration
DPLL_FREQ_HARD_LIMIT[7:0]_CNFG - DPLL Hard Limit Configuration 1
DPLL_FREQ_HARD_LIMIT[15:8]_CNFG - DPLL Hard Limit Configuration 2
Programming Information
Address: 65H
Type: Read / Write
Default Value: 10001100
IDT82V3352
Address: 66H
Type: Read / Write
Default Value: 10101011
Address: 67H
Type: Read / Write
Default Value: 00011001
DPLL_FREQ_H
DPLL_FREQ_H
FREQ_LIMT_P
ARD_LIMT15
6 - 0
ARD_LIMT7
Bit
7 - 0
7 - 0
7
Bit
Bit
H_LOS
7
7
7
DPLL_FREQ_SOFT_LIMT[6:0]
DPLL_FREQ_HARD_LIMT[15:8]
DPLL_FREQ_HARD_LIMT[7:0] Refer to the description of the DPLL_FREQ_HARD_LIMT[15:8] bits (b7~0, 67H).
FREQ_LIMT_PH_LOS
DPLL_FREQ_S
DPLL_FREQ_H
DPLL_FREQ_H
ARD_LIMT14
OFT_LIMT6
ARD_LIMT6
Name
6
6
Name
6
Name
DPLL_FREQ_S
DPLL_FREQ_H
DPLL_FREQ_H
ARD_LIMT13
OFT_LIMT5
ARD_LIMT5
This bit determines whether the T0 DPLL in hard alarm status will result in it unlocked.
0: Disabled.
1: Enabled. (default)
These bits represent an unsigned integer. If the value is multiplied by 0.724, the DPLL soft limit for T0 path in ppm will
be gotten.
The DPLL soft limit is symmetrical about zero.
5
5
5
The DPLL_FREQ_HARD_LIMT[15:0] bits represent an unsigned integer. If the value is multiplied by 0.0014, the
DPLL hard limit for T0 path in ppm will be gotten.
The DPLL hard limit is symmetrical about zero.
DPLL_FREQ_S
DPLL_FREQ_H
DPLL_FREQ_H
ARD_LIMT12
ARD_LIMT4
OFT_LIMT4
4
4
4
94
DPLL_FREQ_S
DPLL_FREQ_H
DPLL_FREQ_H
ARD_LIMT11
OFT_LIMT3
ARD_LIMT3
3
3
3
Description
Description
Description
DPLL_FREQ_S
DPLL_FREQ_H
DPLL_FREQ_H
ARD_LIMT10
OFT_LIMT2
ARD_LIMT2
2
2
2
SYNCHRONOUS ETHERNET WAN PLL
DPLL_FREQ_S
DPLL_FREQ_H
DPLL_FREQ_H
ARD_LIMT1
ARD_LIMT9
OFT_LIMT1
1
1
1
DPLL_FREQ_S
DPLL_FREQ_H
DPLL_FREQ_H
March 23, 2009
ARD_LIMT0
ARD_LIMT8
OFT_LIMT0
0
0
0