82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 95

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

CURRENT_DPLL_PHASE[7:0]_STS - DPLL Current Phase Status 1 *
CURRENT_DPLL_PHASE[15:8]_STS - DPLL Current Phase Status 2 *
T0_T4_APLL_BW_CNFG - T0 / T4 APLL Bandwidth Configuration
Programming Information
Address: 68H
Type: Read
Default Value: 00000000
IDT82V3352
Address: 69H
Type: Read
Default Value: 00000000
Address: 6AH
Type: Read / Write
Default Value: XX01XX01
CURRENT_PH
CURRENT_PH
7 - 0
_DATA15
7 - 0
_DATA7
7 - 6
5 - 4
3 - 2
1 - 0
Bit
Bit
Bit
7
7
7
-
CURRENT_PH_DATA[15:8]
CURRENT_PH_DATA[7:0] Refer to the description of the CURRENT_PH_DATA[15:8] bits (b7~0, 69H).
T0_APLL_BW[1:0]
T4_APLL_BW[1:0]
CURRENT_PH
CURRENT_PH
Name
_DATA14
_DATA6
-
-
Name
Name
6
6
6
-
Reserved.
These bits set the bandwidth for T0 APLL.
00: 100 kHz.
01: 500 kHz. (default)
10: 1 MHz.
11: 2 MHz.
Reserved.
These bits set the bandwidth for T4 APLL.
00: 100 kHz.
01: 500 kHz. (default)
10: 1 MHz.
11: 2 MHz.
CURRENT_PH
CURRENT_PH
T0_APLL_BW1
_DATA13
_DATA5
The CURRENT_PH_DATA[15:0] bits represent a 2’s complement signed integer. If the value is multiplied by 0.61, the
averaged phase error of the T0 DPLL feedback with respect to the selected input clock in ns will be gotten.
5
5
5
CURRENT_PH
CURRENT_PH
T0_APLL_BW0
_DATA12
_DATA4
4
4
4
95
CURRENT_PH
CURRENT_PH
_DATA11
_DATA3
3
3
3
-
Description
Description
Description
CURRENT_PH
CURRENT_PH
_DATA10
_DATA2
2
2
2
-
SYNCHRONOUS ETHERNET WAN PLL
CURRENT_PH
CURRENT_PH
T4_APLL_BW1
_DATA1
_DATA9
1
1
1
CURRENT_PH
CURRENT_PH
T4_APLL_BW0
March 23, 2009
_DATA0
_DATA8
0
0
0