82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 20

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

3.6
input clock selection, as shown in
Table 6: Input Clock Selection for T0 Path
IN2_CMOS/IN2_DIFF pairs.
ity monitoring and the related registers configuration.
3.6.1
Fast selection, only IN1_CMOS/IN1_DIFF and IN2_CMOS/IN2_DIFF
pairs are available for selection. Refer to
Functional Description
Table 7: External Fast Selection
IDT82V3352
The EXT_SW bit and the T0_INPUT_SEL[3:0] bits determine the
External Fast selection is done between IN1_CMOS/IN1_DIFF and
Forced selection is done by setting the related registers.
Automatic selection is done based on the results of input clocks qual-
The selected input clock is attempted to be locked in T0 DPLL.
The External Fast selection is supported by T0 path only. In External
FF_SRCSW (after reset)
EXT_SW
1
0
DPLL INPUT CLOCK SELECTION
EXTERNAL FAST SELECTION
Control Bits
high
low
T0_INPUT_SEL[3:0]
other than 0000
don’t-care
0000
IN1_CMOS_SEL_PRIORITY[3:0]
Table
6:
other than 0000
Figure
Control Pin & Bits
don’t-care
Input Clock Selection
External Fast selection
0000
Automatic selection
Forced selection
5. The results of input
IN2_CMOS_SEL_PRIORITY[3:0]
20
clocks quality monitoring (refer to
toring) do not affect input clock selection.
after reset (this pin determines the default value of the EXT_SW bit dur-
ing
IN1_CMOS_SEL_PRIORITY[3:0]
IN2_CMOS_SEL_PRIORITY[3:0] bits, as shown in
Table
other than 0000
The T0 input clock selection is determined by the FF_SRCSW pin
don’t-care
0000
7:
reset,
IN1_CMOS
IN2_CMOS
IN2_DIFF
IN1_DIFF
IN1_CMOS_SEL_PRIORITY[3:0] bits
Figure 5. External Fast Selection
IN2_CMOS_SEL_PRIORITY[3:0] bits
refer
to
SYNCHRONOUS ETHERNET WAN PLL
Chapter 2
FF_SRCSW pin
Chapter 3.5 Input Clock Quality Moni-
the Selected Input Clock
bits
IN1_CMOS
IN2_CMOS
IN1_DIFF
IN2_DIFF
Pin
locked in T0 DPLL
attempted to be
Description),
March 23, 2009
and
Figure 5
and
the
the