82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 69

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

6.2.4
FREQ_MON_FACTOR_CNFG - Factor of Frequency Monitor Configuration
ALL_FREQ_MON_THRESHOLD_CNFG - Frequency Monitor Threshold for All Input Clocks Configuration
Programming Information
IDT82V3352
Address: 2FH
Type: Read / Write
Default Value: XXXX0011
Address: 2EH
Type: Read / Write
Default Value: XXXX1011
7 - 4
3 - 0
7 - 4
3 - 0
Bit
Bit
7
-
7
-
INPUT CLOCK QUALITY MONITORING CONFIGURATION & STATUS REGISTERS
ALL_FREQ_HARD_THRESHOLD[3:0]
FREQ_MON_FACTOR[3:0]
6
-
Name
6
-
-
Name
-
5
-
Reserved.
These bits determine a factor. The factor has a relationship with the frequency hard alarm threshold in ppm (refer to
the description of the ALL_FREQ_HARD_THRESHOLD[3:0] bits (b3~0, 2FH)) and with the frequency of the input
clock with respect to the master clock in ppm (refer to the description of the IN_FREQ_VALUE[7:0] bits (b7~0, 42H)).
The factor represents the accuracy of the frequency monitor and should be set according to the requirements of differ-
ent applications.
0000: 0.0032.
0001: 0.0064.
0010: 0.0127.
0011: 0.0257.
0100: 0.0514.
0101: 0.103.
0110: 0.206.
0111: 0.412.
1000: 0.823.
1001: 1.646.
1010: 3.292.
1011: 3.81. (default)
1100 - 1111: 4.6.
5
-
4
Reserved.
These bits represent an unsigned integer. The frequency hard alarm threshold in ppm can be calculated as
follows:
Frequency Hard Alarm Threshold (ppm) = (ALL_FREQ_HARD_THRESHOLD[3:0] + 1) X
FREQ_MON_FACTOR[3:0] (b3~0, 2EH)
This threshold is symmetrical about zero.
-
ALL_FREQ_HARD_
4
-
THRESHOLD3
3
69
FREQ_MON_F
ACTOR3
3
ALL_FREQ_HARD_
THRESHOLD2
Description
2
FREQ_MON_F
Description
ACTOR2
2
SYNCHRONOUS ETHERNET WAN PLL
ALL_FREQ_HARD_
THRESHOLD1
FREQ_MON_F
1
ACTOR1
1
ALL_FREQ_HARD_
THRESHOLD0
FREQ_MON_F
March 23, 2009
ACTOR0
0
0