82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 46

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

Table 30: Register List and Map (Continued)
Programming Information
IDT82V3352
Address
(Hex)
5E
6A
6D
7A
7B
7C
5F
60
62
63
64
65
66
67
68
69
71
72
73
74
78
T0_HOLDOVER_FREQ[15:8]_CNFG
- T0 DPLL Holdover Frequency Con-
figuration 2
T0_HOLDOVER_FREQ[23:16]_CNFG
- T0 DPLL Holdover Frequency Con-
figuration 3
DPLL_APLL_PATH_CNFG - DPLL &
APLL Path Configuration
CURRENT_DPLL_FREQ[7:0]_STS -
DPLL Current Frequency Status 1 *
CURRENT_DPLL_FREQ[15:8]_STS -
DPLL Current Frequency Status 2 *
CURRENT_DPLL_FREQ[23:16]_STS
- DPLL Current Frequency Status 3 *
DPLL_FREQ_SOFT_LIMIT_CNFG
DPLL Soft Limit Configuration
DPLL_FREQ_HARD_LIMIT[7:0]_CNF
G - DPLL Hard Limit Configuration 1
DPLL_FREQ_HARD_LIMIT[15:8]_CN
FG - DPLL Hard Limit Configuration 2
CURRENT_DPLL_PHASE[7:0]_STS -
DPLL Current Phase Status 1 *
CURRENT_DPLL_PHASE[15:8]_STS
- DPLL Current Phase Status 2 *
T0_T4_APLL_BW_CNFG - T0 / T4
APLL Bandwidth Configuration
OUT2_FREQ_CNFG - Output Clock 2
Frequency Configuration
OUT1_FREQ_CNFG - Output Clock 1
Frequency Configuration
OUT1_INV_CNFG - Output Clock 1
Invert Configuration
OUT2_INV_CNFG - Output Clock 2
Invert Configuration
FR_MFR_SYNC_CNFG - Frame Sync
& Multiframe Sync Output Configura-
tion
PHASE_MON_PBO_CNFG - Phase
Transient Monitor & PBO Configura-
tion
PHASE_OFFSET[7:0]_CNFG - Phase
Offset Configuration 1
PHASE_OFFSET[9:8]_CNFG - Phase
Offset Configuration 2
SYNC_MONITOR_CNFG - Sync Mon-
itor Configuration
Register Name
-
T_PH_LOS
IN_2K_4K_
FREQ_LIM
_WINDOW
IN_NOISE
PH_OFFS
SYNC_BY
8K_INV
ET_EN
PASS
Bit 7
-
-
-
Synchronization Configuration Registers
PBO & Phase Offset Control Registers
OUT2_PATH_SEL[3:0]
OUT1_PATH_SEL[3:0]
T4_APLL_PATH[3:0]
Output Configuration Registers
8K_EN
Bit 6
-
-
-
-
-
SYNC_MON_LIMT[2:0]
PH_MON_
2K_EN
T0_APLL_BW[1:0]
Bit 5
EN
46
-
-
-
DPLL_FREQ_HARD_LIMT[15:8]
CURRENT_DPLL_FREQ[23:16]
DPLL_FREQ_HARD_LIMT[7:0]
T0_HOLDOVER_FREQ[23:16]
CURRENT_DPLL_FREQ[15:8]
T0_HOLDOVER_FREQ[15:8]
CURRENT_DPLL_FREQ[7:0]
CURRENT_PH_DATA[15:8]
CURRENT_PH_DATA[7:0]
2K_8K_PU
PH_MON_
L_POSITI
PBO_EN
DPLL_FREQ_SOFT_LIMT[6:0]
Bit 4
PH_OFFSET[7:0]
ON
-
-
-
8K_INV
Bit 3
-
-
-
-
-
-
PH_TR_MON_LIMT[3:0]
SYNCHRONOUS ETHERNET WAN PLL
OUT2_INV
8K_PUL
OUT2_DIVIDER[3:0]
OUT1_DIVIDER[3:0]
Bit 2
-
-
-
-
OUT1_INV
2K_INV
T4_APLL_BW[1:0]
Bit 1
PH_OFFSET[9:8]
-
-
-
2K_PUL
Bit 0
March 23, 2009
-
-
-
Reference
P 100
P 101
Page
P 92
P 92
P 92
P 93
P 93
P 93
P 94
P 94
P 94
P 95
P 95
P 95
P 96
P 96
P 97
P 97
P 98
P 99
P 99