82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 41

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

5
dard except the following:
Table 29: JTAG Timing Characteristics
JTAG
IDT82V3352
This device is compliant with the IEEE 1149.1 Boundary Scan stan-
The JTAG interface timing diagram is shown in
• The output boundary scan cells do not capture data from the
• The TRST pin is set low by default and JTAG is disabled in order
Symbol
core and the device does not support EXTEST instruction;
to be consistent with other manufacturers.
t
TCK
t
t
t
S
H
D
TCK
TMS
TDI
JTAG
TMS / TDI to TCK setup time
TCK to TMS / TDI Hold Time
TCK to TDO delay time
TCK period
Parameter
TDO
t
S
Figure 16. JTAG Interface Timing Diagram
Figure
16.
t
H
41
t
TCK
Min
100
25
25
t
D
Typ
SYNCHRONOUS ETHERNET WAN PLL
Max
50
March 23, 2009
Unit
ns
ns
ns
ns