82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 5

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

List of Tables
Table 1: Pin Description ............................................................................................................................................................................................. 11
Table 2: Related Bit / Register in Chapter 3.2 ........................................................................................................................................................... 15
Table 3: Related Bit / Register in Chapter 3.3 ........................................................................................................................................................... 16
Table 4: Related Bit / Register in Chapter 3.4 ........................................................................................................................................................... 17
Table 5: Related Bit / Register in Chapter 3.5 ........................................................................................................................................................... 19
Table 6: Input Clock Selection for T0 Path ................................................................................................................................................................ 20
Table 7: External Fast Selection ................................................................................................................................................................................ 20
Table 8: ‘n’ Assigned to the Input Clock ..................................................................................................................................................................... 21
Table 9: Related Bit / Register in Chapter 3.6 ........................................................................................................................................................... 21
Table 10: Coarse Phase Limit Programming (the selected input clock of 2 kHz, 4 kHz or 8 kHz) .............................................................................. 22
Table 11: Coarse Phase Limit Programming (the selected input clock of other than 2 kHz, 4 kHz and 8 kHz) .......................................................... 22
Table 12: Related Bit / Register in Chapter 3.7 ........................................................................................................................................................... 23
Table 13: Conditions of Qualified Input Clocks Available for T0 Selection ................................................................................................................. 24
Table 14: Related Bit / Register in Chapter 3.8 ........................................................................................................................................................... 25
Table 15: T0 DPLL Operating Mode Control ............................................................................................................................................................... 26
Table 16: Frequency Offset Control in Temp-Holdover Mode ..................................................................................................................................... 28
Table 17: Frequency Offset Control in Holdover Mode ............................................................................................................................................... 29
Table 18: Holdover Frequency Offset Read ................................................................................................................................................................ 29
Table 19: Related Bit / Register in Chapter 3.12 ......................................................................................................................................................... 31
Table 20: Outputs on OUT1 & OUT2 if Derived from T0 DPLL Outputs ..................................................................................................................... 31
Table 21: Outputs on OUT1 & OUT2 if Derived from T0 APLL ................................................................................................................................... 32
Table 22: Outputs on OUT1 & OUT2 if Derived from T4 APLL ................................................................................................................................... 33
Table 23: Frame Sync Input Signal Selection .............................................................................................................................................................. 34
Table 24: Synchronization Control ............................................................................................................................................................................... 34
Table 25: Related Bit / Register in Chapter 3.13 ......................................................................................................................................................... 35
Table 26: Related Bit / Register in Chapter 3.14 ......................................................................................................................................................... 36
Table 27: Read Timing Characteristics in Serial Mode ................................................................................................................................................ 40
Table 28: Write Timing Characteristics in Serial Mode ................................................................................................................................................ 40
Table 29: JTAG Timing Characteristics ....................................................................................................................................................................... 41
Table 30: Register List and Map .................................................................................................................................................................................. 42
Table 31: Power Consumption and Maximum Junction Temperature ....................................................................................................................... 103
Table 32: Thermal Data ............................................................................................................................................................................................. 103
Table 33: Absolute Maximum Rating ......................................................................................................................................................................... 104
Table 34: Recommended Operation Conditions ........................................................................................................................................................ 104
Table 35: CMOS Input Port Electrical Characteristics ............................................................................................................................................... 105
Table 36: CMOS Input Port with Internal Pull-Up Resistor Electrical Characteristics ................................................................................................ 105
Table 37: CMOS Input Port with Internal Pull-Down Resistor Electrical Characteristics ........................................................................................... 105
Table 38: CMOS Output Port Electrical Characteristics ............................................................................................................................................ 105
Table 39: PECL Input / Output Port Electrical Characteristics ................................................................................................................................... 107
Table 40: LVDS Input / Output Port Electrical Characteristics ................................................................................................................................... 108
Table 41: Output Clock Jitter Generation .................................................................................................................................................................. 109
Table 42: Output Clock Phase Noise ......................................................................................................................................................................... 110
Table 43: Input Jitter Tolerance (155.52 MHz) .......................................................................................................................................................... 111
Table 44: Input Jitter Tolerance (1.544 MHz) ............................................................................................................................................................ 111
Table 45: Input Jitter Tolerance (2.048 MHz) ............................................................................................................................................................ 111
Table 46: Input Jitter Tolerance (8 kHz) .................................................................................................................................................................... 111
Table 47: T0 DPLL Jitter Transfer & Damping Factor ............................................................................................................................................... 111
Table 48: Input/Output Clock Timing ......................................................................................................................................................................... 113
Table 49: Output Clock Timing .................................................................................................................................................................................. 115
List of Tables
5
March 23, 2009