82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 18

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

3.5
lowing aspects:
selected input clocks have to be monitored further. Refer to
Selected Input Clock Monitoring
3.5.1
as shown in
The input clock is monitored for each period of 128 ms and the internal
leaky bucket accumulator increases by 1 when an event is detected; it
decreases by 1 if no event is detected within the period set by the decay
rate. The event is that an input clock drifts outside (>) ±500 ppm with
respect to the master clock within a 128 ms period.
The leaky bucket configuration for an input clock is selected by the cor-
Functional Description
IDT82V3352
Leaky Bucket Accumulator
The qualities of all the input clocks are always monitored in the fol-
The qualified clocks are available for T0 DPLL selection. The T0
Activity is monitored by using an internal leaky bucket accumulator,
Each input clock is assigned an internal leaky bucket accumulator.
There are four configurations (0 - 3) for a leaky bucket accumulator.
No-activity Alarm Indication
• Activity
• Frequency
Input Clock
INPUT CLOCK QUALITY MONITORING
ACTIVITY MONITORING
Figure
4.
for details.
clock signal with no event
Figure 4. Input Clock Activity Monitoring
Decay
Rate
Chapter 3.7
18
responding BUCKET_SEL[1:0] bits. Each leaky bucket configuration
consists of four elements: upper threshold, lower threshold, bucket size
and decay rate.
the accumulated events reach the bucket size, the accumulator will stop
increasing even if further events are detected. The upper threshold is a
point above which a no-activity alarm is raised. The lower threshold is a
point below which the no-activity alarm is cleared. The decay rate is a
certain period during which the accumulator decreases by 1 if no event
is detected.
of register bits: the BUCKET_SIZE_n_DATA[7:0] bits, the UPPER_
THRESHOLD_n_DATA[7:0]
DATA[7:0] bits and the DECAY_RATE_n_DATA[1:0] bits respectively; ‘n’
is 0 ~ 3.
INn_CMOS_NO_ACTIVITY_ALARM bit (n = 1, 2, or 3) /
INn_DIFF_NO_ACTIVITY_ALARM bit (n = 1 or 2).
tion for T0 DPLL.
clock signal with events
The bucket size is the capability of the accumulator. If the number of
The leaky bucket configuration is programmed by one of four groups
The no-activity alarm status of the input clock is indicated by the
The input clock with a no-activity alarm is disqualified for clock selec-
SYNCHRONOUS ETHERNET WAN PLL
bits,
the
LOWER_THRESHOLD_n_
March 23, 2009
Bucket Size
Upper Threshold
Lower Threshold
0