82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 31

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

3.12
performance of the device output clocks.
/ T4_APLL_BW[1:0] bits respectively. The lower the bandwidth is, the
better the jitter and wander performance of the T0/T4 APLL output are.
puts, as selected by the T0_APLL_PATH[3:0] / T4_APLL_PATH[3:0] bits
respectively.
device output.
Table 19: Related Bit / Register in Chapter 3.12
Table 20: Outputs on OUT1 & OUT2 if Derived from T0 DPLL Outputs
Functional Description
IDT82V3352
Note:
1. n = 1 or 2. Each output is assigned a frequency divider.
2. E1 = 2.048 MHz, T1 = 1.544 MHz, E3 = 34.368 MHz, T3 = 44.736 MHz. The blank cell means the configuration is reserved.
OUTn_DIVIDER[3:0]
T0_APLL_PATH[3:0]
T4_APLL_PATH[3:0]
(Output Divider)
T0_APLL_BW[1:0]
T4_APLL_BW[1:0]
A T0 APLL and a T4 APLL are provided for a better jitter and wander
The bandwidths of the T0/T4 APLL are set by the T0_APLL_BW[1:0]
The input of the T0/T4 APLL can be derived from the T0 DPLL out-
Both the APLL and DPLL outputs are provided for selection for the
0000
0001
0010
0011
0100
0101
0110
1000
1001
1010
1011
1100
1101
0111
1110
1111
Bit
T0 / T4 APLL
1
77.76 MHz
64 kHz
400 Hz
T0_DPLL_APLL_PATH_CNFG
8 kHz
2 kHz
1Hz
DPLL_APLL_PATH_CNFG
T0_T4_APLL_BW_CNFG
Register
12E1
12E1
6E1
3E1
2E1
E1
16E1
16E1
8E1
4E1
2E1
E1
outputs on OUT1 & OUT2 if derived from T0 DPLL outputs
Address (Hex)
6A
55
60
24T1
24T1
12T1
6T1
4T1
3T1
2T1
T1
Output is disabled (output high).
Output is disabled (output low).
31
16T1
16T1
3.13
altogether.
3.13.1
OUT1_PECL_LVDS bit. OUT2 outputs a CMOS signal.
nals derived from the T0 DPLL and T0/T4 APLL outputs, and the corre-
sponding OUTn_PATH_SEL[3:0] bits (n = 1 or 2). The derived signal can
be from the T0 DPLL and T0/T4 APLL outputs, as selected by the corre-
sponding OUTn_PATH_SEL[3:0] bits (n = 1 or 2). If the signal is derived
from one of the T0 DPLL outputs, please refer to
frequency. If the signal is derived from the T0/T4 APLL output, please
refer to
the corresponding OUTn_INV bit (n = 1 or 2).
aligned with the T0/T4 selected input clock respectively every 125 µs
period.
8T1
4T1
2T1
T1
The device supports 2 output clocks and 2 frame sync output signals
The device provides 2 output clocks.
OUT1 outputs a PECL or LVDS signal, as selected by the
The outputs on OUT1 and OUT2 are variable, depending on the sig-
The outputs on OUT1 and OUT2 can be inverted, as determined by
Both the output clocks derived from T0/T4 selected input clock are
Table 21~Table 22
OUTPUT CLOCKS & FRAME SYNC SIGNALS
OUTPUT CLOCKS
E3
E3
T3
T3
SYNCHRONOUS ETHERNET WAN PLL
for the output frequency.
(26 MHz)
2
13 MHz
GSM
(30.72 MHz)
15.36 MHz
Table 20
OBSAI
March 23, 2009
for the output
(40 MHz)
GPS
20
10
5