82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 4

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

Table of Contents
4 MICROPROCESSOR INTERFACE .................................................................................................................................. 39
5 JTAG ................................................................................................................................................................................ 41
6 PROGRAMMING INFORMATION .................................................................................................................................... 42
7 THERMAL MANAGEMENT ........................................................................................................................................... 103
8 ELECTRICAL SPECIFICATIONS .................................................................................................................................. 104
PACKAGE DIMENSIONS.................................................................................................................................................... 120
ORDERING INFORMATION................................................................................................................................................ 125
IDT82V3352
3.11 DPLL OUTPUT .............................................................................................................................................................................................. 30
3.12 T0 / T4 APLL ................................................................................................................................................................................................. 31
3.13 OUTPUT CLOCKS & FRAME SYNC SIGNALS ........................................................................................................................................... 31
3.14 INTERRUPT SUMMARY ............................................................................................................................................................................... 36
3.15 T0 SUMMARY ............................................................................................................................................................................................... 36
3.16 POWER SUPPLY FILTERING TECHNIQUES ............................................................................................................................................. 37
3.17 LINE CARD APPLICATION .......................................................................................................................................................................... 38
6.1 REGISTER MAP ............................................................................................................................................................................................ 42
6.2 REGISTER DESCRIPTION ........................................................................................................................................................................... 47
7.1 JUNCTION TEMPERATURE ...................................................................................................................................................................... 103
7.2 EXAMPLE OF JUNCTION TEMPERATURE CALCULATION ................................................................................................................... 103
7.3 HEATSINK EVALUATION .......................................................................................................................................................................... 103
8.1 ABSOLUTE MAXIMUM RATING ................................................................................................................................................................ 104
8.2 RECOMMENDED OPERATION CONDITIONS .......................................................................................................................................... 104
8.3 I/O SPECIFICATIONS ................................................................................................................................................................................. 105
8.4 JITTER & WANDER PERFORMANCE ....................................................................................................................................................... 109
8.5 OUTPUT WANDER GENERATION ............................................................................................................................................................ 112
8.6 INPUT / OUTPUT CLOCK TIMING ............................................................................................................................................................. 113
8.7 OUTPUT CLOCK TIMING ........................................................................................................................................................................... 114
3.11.1 PFD Output Limit ............................................................................................................................................................................ 30
3.11.2 Frequency Offset Limit .................................................................................................................................................................. 30
3.11.3 PBO ................................................................................................................................................................................................. 30
3.11.4 Phase Offset Selection .................................................................................................................................................................. 30
3.11.5 Four Paths of T0 DPLL Outputs .................................................................................................................................................... 30
3.13.1 Output Clocks ................................................................................................................................................................................. 31
3.13.2 Frame SYNC Output Signals ......................................................................................................................................................... 34
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.2.10 Synchronization Configuration Registers ................................................................................................................................. 101
8.3.1
8.3.2
3.10.1.6 Pre-Locked2 Mode ........................................................................................................................................................... 29
3.11.5.1 T0 Path ............................................................................................................................................................................. 30
Global Control Registers ............................................................................................................................................................... 47
Interrupt Registers ......................................................................................................................................................................... 54
Input Clock Frequency & Priority Configuration Registers ....................................................................................................... 58
Input Clock Quality Monitoring Configuration & Status Registers ........................................................................................... 69
T0 DPLL Input Clock Selection Registers .................................................................................................................................... 80
T0 DPLL State Machine Control Registers .................................................................................................................................. 83
T0 DPLL & APLL Configuration Registers ................................................................................................................................... 85
Output Configuration Registers .................................................................................................................................................... 96
PBO & Phase Offset Control Registers ........................................................................................................................................ 99
CMOS Input / Output Port ............................................................................................................................................................ 105
PECL / LVDS Input / Output Port ................................................................................................................................................ 106
8.3.2.1
8.3.2.2
3.10.1.5.1 Automatic Instantaneous ............................................................................................................................... 29
3.10.1.5.2 Automatic Slow Averaged ............................................................................................................................. 29
3.10.1.5.3 Automatic Fast Averaged .............................................................................................................................. 29
3.10.1.5.4 Manual ........................................................................................................................................................... 29
3.10.1.5.5 Holdover Frequency Offset Read .................................................................................................................. 29
PECL Input / Output Port ................................................................................................................................................ 106
LVDS Input / Output Port ................................................................................................................................................ 108
4
SYNCHRONOUS ETHERNET WAN PLL
March 23, 2009