82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 51

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

DIFFERENTIAL_IN_OUT_OSCI_CNFG - Differential Input / Output Port & Master Clock Configuration
Programming Information
IDT82V3352
Address: 0AH
Type: Read / Write
Default Value: XXXXX00X
7 -3
Bit
2
1
0
7
-
OUT1_PECL_LVDS
OSC_EDGE
Name
-
-
6
-
Reserved.
This bit selects a better active edge of the master clock.
0: The rising edge. (default)
1: The falling edge.
This bit selects a port technology for OUT1.
0: LVDS. (default)
1: PECL.
Reserved
5
-
4
-
51
3
-
Description
OSC_EDGE
2
SYNCHRONOUS ETHERNET WAN PLL
OUT1_PECL_LVDS
1
March 23, 2009
0
-