82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 25

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

Table 14: Related Bit / Register in Chapter 3.8
HIGHEST_PRIORITY_VALIDATED[3:0] bits. See
assigned to the input clock.
switch
Functional Description
IDT82V3352
INn_CMOS_NO_ACTIVITY_ALARM (n = 1, 2 or 3)
INn_CMOS_FREQ_HARD_ALARM (n = 1, 2 or 3)
When the device is configured in Automatic selection and Revertive
INn_CMOS
INn_CMOS
INn_CMOS
INn_DIFF_NO_ACTIVITY_ALARM (n = 1 or 2)
INn_DIFF_FREQ_HARD_ALARM (n = 1 or 2)
INn_CMOS_PH_LOCK_ALARM (
INn_CMOS_SEL_PRIORITY[3:0] (n = 1, 2 or 3)
INn_DIFF_SEL_PRIORITY[3:0] (n = 1 or 2)
INn_DIFF_PH_LOCK_ALARM (n = 1 or 2)
is
HIGHEST_PRIORITY_VALIDATED[3:0]
CURRENTLY_SELECTED_INPUT[3:0]
SECOND_PRIORITY_VALIDATED[3:0]
THIRD_PRIORITY_VALIDATED[3:0]
enabled,
1
2
3
T0_MAIN_REF_FAILED
T0_MAIN_REF_FAILED
(n = 1, 2 or 3) / INn_DIFF
(n = 1, 2 or 3) / INn_DIFF
(n = 1, 2 or 3) / INn_DIFF
LOS_FLAG_TO_TDO
IN_NOISE_WINDOW
REVERTIVE_MODE
ULTR_FAST_SW
Bit
the
input
n = 1, 2 or 3
1
2
1
2
3
(n = 1 or 2)
(n = 1 or 2)
(n = 1 or 2)
clock
)
indicated
Table 8
IN1_IN2_CMOS_SEL_PRIORITY_CNFG, IN3_CMOS_SEL_PRIORITY_CNFG
for the ‘n’
INTERRUPTS1_ENABLE_CNFG, INTERRUPTS2_ENABLE_CNFG
by
the
INPUT_VALID1_STS, INPUT_VALID2_STS
INTERRUPTS1_STS, INTERRUPTS2_STS
25
IN1_IN2_CMOS_STS, IN3_CMOS_STS
IN1_IN2_DIFF_SEL_PRIORITY_CNFG
CURRENTLY_SELECTED_INPUT[3:0] bits is the same as the one indi-
cated by the HIGHEST_PRIORITY_VALIDATED[3:0] bits; otherwise,
they are not the same.
INTERRUPTS2_ENABLE_CNFG
PHASE_MON_PBO_CNFG
PRIORITY_TABLE1_STS
PRIORITY_TABLE2_STS
MON_SW_PBO_CNFG
INPUT_MODE_CNFG
INTERRUPTS2_STS
IN1_IN2_DIFF_STS
Register
SYNCHRONOUS ETHERNET WAN PLL
March 23, 2009
Address (Hex)
27 *, 2A *
4A, 4B
0D, 0E
10, 11
44, 47
4E *
28 *
4F *
0B
45
78
0E
09
11