82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 37

• Manufacturer Part Number: 82V3352EDG
• Description: SYNCHRONOUS ETHERNET WAN PLL
• Manufacturer: IDT [Integrated Device Technology]

3.16
required to minimize supply noise modulation of the output clocks. The
common sources of power supply noise are switch power supplies and
the high switching noise from the outputs to the internal PLL. The
IDT82V3352 provides separate VDDA power pins for the internal analog
PLL, VDD_DIFF for the differential output driver circuit and VDDD pins
for the core logic as well as I/O driver circuits.
ing regulator, the power supply output should be filtering with sufficient
bulk capacity to minimize ripple and 0.1 uF (0402 case size, ceramic)
caps to filter out the switching transients.
VDDD are handled individually. VDDD, VDD_DIFF and VDDA should be
individually connected to the power supply plane through vias, and
bypass capacitors should be used for each pin.
bypass capacitor and ferrite bead should be connected to power pins.
Functional Description
IDT82V3352
To achieve optimum jitter performance, power supply filtering is
To minimize switching power supply noise generated by the switch-
For the IDT82V3352, the decoupling for VDDA, VDD_DIFF and
3.3V
SLF7028T-100M1R1
POWER SUPPLY FILTERING TECHNIQUES
10 µF
0.1 µF
3. 3V
0.1 µF
SLF7028T-100M1R1
0.1 µF
Figure 11. IDT82V3352 Power Decoupling Scheme
Figure 12
0.1 µF
10 µF
0.1 µF
illustrated how
0.1 µ F
0.1 µ F
0.1 µF
0.1 µF
37
0 .1 µF
0.1 µF
impedance. This can be achieved by using one 10 uF (1210 case size,
ceramic) and at least four 0.1 uF (0402 case size, ceramic) capacitors in
parallel. The 0.1 uF (0402 case size, ceramic) capacitors must be
placed right next to the VDDA and VDD_DIFF pins as close as possible.
Note that the 10 uF capacitor must be of 1210 case size, and it must be
ceramic for lowest ESR (Effective Series Resistance) possible. The 0.1
uF should be of case size 0402, this offers the lowest ESL (Effective
Series Inductance) to achieve low impedance towards the high speed
range.
uF (1210 case size, ceramic) capacitors are recommended. The 0.1 uF
capacitors should be placed as close to the VDDD pins as possible.
0.1 µF
The analog power supply VDDA and VDD_DIFF should have low
For VDDD, at least ten 0.1 uF (0402 case size, ceramic) and one 10
Please refer to evaluation board schematic for details.
0.1 µF
VDD _DIFF
VDDD
0.1 µF
VDDA
IDT 82 V3352
4, 14, 57
22
8, 9, 12, 32, 36, 38, 39, 45, 46 , 54
SYNCHRONOUS ETHERNET WAN PLL
7, 10, 11, 31, 40, 53
1, 3, 15, 58
21
March 23, 2009
AGND
DGND
GND_DIFF