82V3352EDG IDT [Integrated Device Technology], 82V3352EDG Datasheet - Page 35

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82V3352EDG

Manufacturer Part Number
82V3352EDG
Description
SYNCHRONOUS ETHERNET WAN PLL
Manufacturer
IDT [Integrated Device Technology]
Datasheet
Table 25: Related Bit / Register in Chapter 3.13
Functional Description
IDT82V3352
Figure 9. 0.5 UI Late Frame Sync Input Signal Timing
sync input signal
Selected frame
output signals
Output clocks
T0 selected
Frame sync
input clock
OUTn_PATH_SEL[3:0] (n = 1 or 2)
SYNC_PHn[1:0] (n = 1, 2 or 3)
OUTn_DIVIDER[3:0] (n = 1 or 2)
EX_SYNC_ALARM_MON
2K_8K_PUL_POSITION
AUTO_EXT_SYNC_EN
SYNC_MON_LIMT[2:0]
OUTn_INV (n = 1 or 2)
EX_SYNC_ALARM
EX_SYNC_ALARM
OUT1_PECL_LVDS
IN_SONET_SDH
EXT_SYNC_EN
SYNC_BYPASS
8K_PUL
2K_PUL
8K_INV
2K_INV
8K_EN
2K_EN
Bit
1
2
35
OUT1_FREQ_CNFG, OUT2_FREQ_CNFG
DIFFERENTIAL_IN_OUT_OSCI_CNFG
OUT1_INV_CNFG, OUT2_INV_CNFG
Figure 10. 1 UI Late Frame Sync Input Signal Timing
INTERRUPTS3_ENABLE_CNFG
sync input signal
Selected frame
output signals
Output clocks
Frame sync
T0 selected
input clock
SYNC_MONITOR_CNFG
FR_MFR_SYNC_CNFG
SYNC_PHASE_CNFG
INPUT_MODE_CNFG
INTERRUPTS3_STS
OPERATING_STS
Register
SYNCHRONOUS ETHERNET WAN PLL
March 23, 2009
Address (Hex)
71, 6D
73, 72
0A
7C
7D
09
74
52
0F
12

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