R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 993

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

21.3.9
CROMST1 indicates error status in the post-ECC header.
Bit
1
0
Bit
7 to 4
3
2
1
0
Bit Name
ST_SECS
ST_SECL
Bit Name

ER2_HEAD0
ER2_HEAD1
ER2_HEAD2
ER2_HEAD3
Post-ECC Header Error Status Register (CROMST1)
Initial value:
Initial
Value
0
0
Initial
Value
All 0
0
0
0
0
R/W:
Bit:
—
R
7
0
R/W
R
R
R/W
R
R
R
R
R
—
R
6
0
after ECC correction.
Description
Indicates that a sector has been processed as a short
sector with the aid of interpolated sync codes. If this bit
is set to 1, stop decoding immediately and retry the
procedure starting from the sector prior to the currently
being decoded sector.
Indicates that a sector has been processed as a long
sector with the aid of interpolated sync codes. If this bit
is set to 1, stop decoding immediately and retry the
procedure starting from two sectors prior to the sector
currently being decoded.
Description
Reserved
These bits are always read as 0 and cannot be
modified.
Indicates an error status in the minutes field of the
header after ECC correction.
Indicates an error status in the seconds field of the
header after ECC correction.
Indicates an error status in the frames (1/75 second)
field of the header after ECC correction.
Indicates an error status in the mode field of the header
—
R
5
0
—
R
4
0
HEAD0
ER2_
R
3
0
Section 21 CD-ROM Decoder (ROM-DEC)
Rev. 2.00 Sep. 07, 2007 Page 961 of 1312
HEAD1
ER2_
R
2
0
HEAD2
ER2_
R
1
0
HEAD3
ER2_
R
0
0
REJ09B0320-0200