R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 187

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

[Legend]
IRQ
Instruction (instruction replacing
interrupt exception handling)
First instruction in
interrupt service routine
IRQ
First instruction in
interrupt service routine
First instruction in
multiple interrupt service routine
[Legend]
m1:
m2:
m3:
m1:
m2:
m3:
F:
D:
E:
M:
Vector address read
Saving of SR (stack)
Saving of PC (stack)
Vector address read
Saving of SR (stack)
Saving of PC (stack)
Instruction fetch. Instruction is fetched from memory in which program is stored.
Instruction decoding. Fetched instruction is decoded.
Instruction execution. Data operation or address calculation is performed in accordance with the result of decoding.
Memory access. Memory data access is performed.
Figure 6.4 Example of Pipeline Operation when IRQ Interrupt is Accepted
Figure 6.5 Example of Pipeline Operation for Multiple Interrupts
2 Icyc + 3 Bcyc + 1 Pcyc
2 Icyc + 3 Bcyc + 1 Pcyc
Interrupt acceptance
F
(No Register Banking)
(No Register Banking)
Interrupt acceptance
D
F
3 Icyc + m1
E
D
Multiple interrupt acceptance
E
3 Icyc
3 Icyc + m1 + m2
E
m1
M
E
Rev. 2.00 Sep. 07, 2007 Page 155 of 1312
m2
M
D
1 Icyc + m1 + 2(m2) + m3
m1
M
m3
Section 6 Interrupt Controller (INTC)
M
F
E
m2
M
D
E
m3
M
F
m1
M
D
m2
M
REJ09B0320-0200
E
M
F
D