R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 278

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 Bus State Controller (BSC)
1. Ts (Internal Bus Access Start)
2. Tw1 to Twn (Read Cycle Wait, Write Cycle Wait)
3. Tend (First Wait End Cycle)
Rev. 2.00 Sep. 07, 2007 Page 246 of 1312
REJ09B0320-0200
CKIO
A27 to A0
CSn
RD
WR
D31 to D0
This is a bus access request cycle initiated by the internal bus master and with the external bus
as the target. CSn is always high during this cycle. In the next cycle A27 to A0 and the write
data change.
For the first page access, the wait operation from internal bus access start to the wait end cycle
is the same as in normal access.
This is the final cycle in the first series of read cycle wait or write cycle wait cycles. In write
access, the second and subsequent page accesses start from the next cycle, unless a write data
output delay cycle has been specified (with a value other than 0). The RD or WR signal is
negated (high level) in the next cycle if the RD assert wait or WD assert wait setting is other
than 0. If the RD assert wait or WD assert wait setting is 0, the RD or WR signal continues to
be asserted (low level). The CSn signal is not negated and continues to be asserted (low level).
In page read access, the succeeding bus access starts without waiting for the read data sample
cycle (Trd).
Ts
CS assert wait
WR assert wait
Write data
output wait
Tw1 Tw2
Figure 9.5 Basic Bus Timing (Page Write Operation)
Write cycle wait
A0
Bus access (first time)
Twn
D0
Write data output
Tend
Write data output
Tdw1 Tdwn
delay cycle
delay cycle
Tpw1
WR assert wait
and subsequent times)
Write data
output wait
Bus access (second
Page write
cycle wait
A1
Tpwn
Tend
D1
Tdw1 Tdwn
Write data output
delay cycle
CS delay cycle
CS delay cycle
during write
during write
(end only)
Tn1
Tnm