R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 192

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Interrupt Controller (INTC)
Figure 6.12 shows the timing for saving to a register bank. Saving to a register bank takes place
between the start of interrupt exception handling and the start of fetching the first instruction in the
exception service routine.
(2)
The RESBANK (restore from register bank) instruction is used to restore data saved in a register
bank. After restoring data from the register banks with the RESBANK instruction at the end of the
interrupt service routine, execute the RTE instruction to return from exception handling.
Rev. 2.00 Sep. 07, 2007 Page 160 of 1312
REJ09B0320-0200
IRQ
Instruction (instruction replacing
interrupt exception handling)
Overrun fetch
First instruction in
interrupt service routine
[Legend]
m1:
m2:
m3:
Restoration from Bank
Vector address read
Saving of SR (stack)
Saving of PC (stack)
2 Icyc + 3 Bcyc + 1 Pcyc
Figure 6.12 Bank Save Timing
F
D
F
3 Icyc
3 Icyc + m1 + m2
E
Saved to bank
E
(1) VTO, PR, GBR, MACL
m1
M
(2) R12, R13, R14, MACH
m2
M
(3) R8, R9, R10, R11
m3
M
F
(4) R4, R5, R6, R7
E
D
(5) R0, R1, R2, R3
E