R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 937

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

20.3.9
IEMA1 indicates the lower four bits of the communication destination master unit address in
slave/broadcast reception.
IEMA1 is initialized by a power-on reset or in deep standby.
Bit
7 to 4
3 to 0
IEBus Reception Master Address Register 1 (IEMA1)
Bit Name
IMAL4

Initial value:
Initial
Value
0000
All 0
R/W:
Bit:
R
R/W
R
R
7
0
R
6
0
IMAL4
Description
Lower Four Bits of IEBus Reception Master Address
Indicates the lower four bits of the communication
destination master unit address in slave/broadcast
reception. This register is enabled when
slave/broadcast reception starts, and the contents are
changed at the time of setting the RXS flag. If a
broadcast receive error interrupt is selected by the DEE
bit in IECTR and the receive buffer is not in the receive
enabled state at control field reception, a receive error
interrupt is generated and the lower four bits of the
master address are stored in IEMA1.
Reserved
These bits are always read as 0. The write value should
always be 0.
Section 20 IEBus
R
5
0
R
4
0
—
R
3
0
Rev. 2.00 Sep. 07, 2007 Page 905 of 1312
TM
—
R
2
0
Controller (IEB) [R5S72612] [R5S72613]
—
R
1
0
—
R
0
0
REJ09B0320-0200