R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 1331
R5S72611
Manufacturer Part Number
R5S72611
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5S72611.pdf
(1348 pages)
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Table 1.2 Product Lineup
4.4.2 CKIO Control Register
(CKIOCR)
9.5.2 SDRAM Interface
(9) Read/Write Access
(c) Byte Access Control by DQM
Figure 9.26 SDRAMC Setting
Procedure
9.6.2 Write Buffer
9.6.3 Note on Transition to
Software Standby Mode or Deep
Standby Mode
Main Revisions and Additions in this Edition
Page Revision (See Manual for Details)
10
90
264
268
288,
289
Modified
Modified
When this LSI is started in clock operating mode 3, CKIOCR is
initialized to H'00 by a power-on reset caused by the RES pin
or in deep standby mode. When this LSI is started in clock
operating mode 0 or 2, CKIOCR is initialized to H'01 by a
power-on reset caused by the RES pin or in deep standby
mode. This register is not initialized by an internal reset
triggered by an overflow of the WDT, a manual reset, in sleep
mode, or in software standby mode.
Added
Figure modified
Added
Abbreviation
R5S72611
R5S72612
R5S72613
Rev. 2.00 Sep. 07, 2007 Page 1299 of 1312
Main Revisions and Additions in this Edition
Product Code
R5S72611RB120FP
R5S72611RP100FP
R5S72611RP80FP
R5S72612RB120FP
R5S72612RP100FP
R5S72612RP80FP
R5S72613RB120FP
R5S72613RP100FP
R5S72613RP80FP
REJ09B0320-0200
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