R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 868

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
These constraints allow the setting range shown in the table below for TSEG1 and TSEG2 in the
Bit Configuration Register. The number in the table shows possible setting of SJW. "No" shows
that there is no allowed combination of TSEG1 and TSEG2.
Table 19.6 TSG and TSEG Setting
Example 1: To have a Bit rate of 500 Kbps with a frequency of fclk = 40 MHz it is possible to set:
BRP = 3, TSEG1 = 6, TSEG2 = 3.
Then the configuration to write is BCR1 = H'5200 and BCR0 = H'0003.
Example 2: To have a Bit rate of 250 Kbps with a frequency of fclk = 35 MHz it is possible to set:
BRP = 4, TSEG1 = 8, TSEG2 = 5.
Then the configuration to write is BCR1 = H'7400 and BCR0 = H'0004.
Rev. 2.00 Sep. 07, 2007 Page 836 of 1312
REJ09B0320-0200
TSG1
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
TSEG1
4
5
6
7
8
9
10
11
12
13
14
15
16
001
2
No
1-2
1-2
1-2
1-2
1-2
1-2
1-2
1-2
1-2
1-2
1-2
1-2
010
3
1-3
1-3
1-3
1-3
1-3
1-3
1-3
1-3
1-3
1-3
1-3
1-3
1-3
011
4
No
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
100
5
No
No
101
6
No
No
No
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
110
7
No
No
No
No
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
111
8
No
No
No
No
No
TSG2
TSEG2