R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 25

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

20.7 Interrupt Sources................................................................................................................ 939
20.8 Usage Notes ....................................................................................................................... 941
Section 21 CD-ROM Decoder (ROM-DEC).....................................................943
21.1 Features.............................................................................................................................. 943
21.2 Block Diagrams ................................................................................................................. 945
21.3 Register Descriptions ......................................................................................................... 949
20.6.4 Slave Transmit Operation ..................................................................................... 938
20.8.1 Notes when the Communications have not been Completed within the
21.1.1 Formats Supported by ROM-DEC........................................................................ 944
21.3.1 ROM-DEC Enable Control Register (CROMEN) ................................................ 952
21.3.2 Sync Code-Based Synchronization Control Register (CROMSY0) ..................... 953
21.3.3 Decoding Mode Control Register (CROMCTL0) ................................................ 954
21.3.4 EDC/ECC Check Control Register (CROMCTL1) .............................................. 956
21.3.5 Automatic Decoding Stop Control Register (CROMCTL3)................................. 957
21.3.6 Decoding Option Setting Control Register (CROMCTL4) .................................. 958
21.3.7 HEAD20 to HEAD22 Representation Control Register (CROMCTL5) .............. 959
21.3.8 Sync Code Status Register (CROMST0) .............................................................. 960
21.3.9 Post-ECC Header Error Status Register (CROMST1).......................................... 961
21.3.10 Post-ECC Subheader Error Status Register (CROMST3) .................................... 962
21.3.11 Header/Subheader Validity Check Status Register (CROMST4)......................... 963
21.3.12 Mode Determination and Link Sector Detection Status Register
21.3.13 ECC/EDC Error Status Register (CROMST6) ..................................................... 965
21.3.14 Buffer Status Register (CBUFST0) ...................................................................... 966
21.3.15 Decoding Stoppage Source Status Register (CBUFST1) ..................................... 967
21.3.16 Buffer Overflow Status Register (CBUFST2) ...................................................... 968
21.3.17 Pre-ECC Correction Header: Minutes Data Register (HEAD00) ......................... 968
21.3.18 Pre-ECC Correction Header: Seconds Data Register (HEAD01)......................... 969
21.3.19 Pre-ECC Correction Header: Frames (1/75 Second) Data Register
21.3.20 Pre-ECC Correction Header: Mode Data Register (HEAD03)............................. 969
21.3.21 Pre-ECC Correction Subheader: File Number (Byte 16) Data Register
21.3.22 Pre-ECC Correction Subheader: Channel Number (Byte 17) Data Register
21.3.23 Pre-ECC Correction Subheader: Sub-Mode (Byte 18) Data Register
Maximum Number of Transmit Bytes .................................................................. 941
(CROMST5) ......................................................................................................... 964
(HEAD02)............................................................................................................. 969
(SHEAD00) .......................................................................................................... 970
(SHEAD01) .......................................................................................................... 970
(SHEAD02) .......................................................................................................... 971
Rev. 2.00 Sep. 07, 2007 Page xxv of xxxii