R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 721
R5S72611
Manufacturer Part Number
R5S72611
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5S72611.pdf
(1348 pages)
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Bit
2
Bit Name
PER
Initial
Value
0
R/W
R
Section 16 Serial Communication Interface with FIFO (SCIF)
Description
Parity Error Indication
Indicates a parity error in the data read from the next
receive FIFO data register (SCFRDR) in
asynchronous mode.
0: No receive parity error occurred in the next data
[Clearing conditions]
•
•
1: A receive parity error occurred in the next data read
[Setting condition]
•
read from SCFRDR
from SCFRDR
PER is cleared to 0 when the chip undergoes a
power-on reset
PER is cleared to 0 when no parity error is present
in the next data read from SCFRDR
PER is set to 1 when a parity error is present in
the next data read from SCFRDR
Rev. 2.00 Sep. 07, 2007 Page 689 of 1312
REJ09B0320-0200
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