R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 250

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 Bus State Controller (BSC)
To disable the operation for each channel, forcibly write out data tentatively stored in internal
write buffer. The procedure is as follows:
1. Execute read access to the channel whose operation is to be disabled.
2. Then, write 0 to the EXENB bit (operation disabled).
9.4.4
CSMODn selects the mode for page read access and the bit boundary for page access, enables
page read/write access and external wait, and selects the mode for write access.
Rev. 2.00 Sep. 07, 2007 Page 218 of 1312
REJ09B0320-0200
Bit
31
30
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
CSn Mode Register (CSMODn) (n = 0 to 6)
Bit Name
PRMOD

MOD
R/W
PR
—
31
15
R
0
0
—
30
—
14
R
R
0
0
PBCNT[1:0]
R/W
—
29
13
R
0
0
Initial
Value
0
0
R/W
—
28
12
R
0
0
—
27
—
11
R
R
0
0
R/W
R/W
R
—
26
—
10
R
R
0
0
Description
Page Read Access Mode Select
This bit selects the operating mode for page read
access. Clearing PRMOD to 0 selects the normal
access compatible mode. In this mode the RD signal is
negated each time a unit of data is read and an RD
assert wait is inserted. Setting PRMOD to 1 selects the
external data read sequential assert mode. In this
mode RD is asserted continuously between page
accesses.
0: Normal access compatible mode
1: External data read sequential assert mode
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W
ENB
PW
—
25
R
0
9
0
R/W
ENB
PR
—
24
R
0
8
0
—
23
—
R
R
0
7
0
22
—
—
R
R
0
6
0
21
—
—
R
R
0
5
0
20
—
—
R
R
0
4
0
R/W
ENB
EW
19
—
R
0
3
0
18
—
—
R
R
0
2
0
17
—
—
R
R
0
1
0
MOD
R/W
WR
16
—
R
0
0
0