R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 274

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 Bus State Controller (BSC)
9.5
9.5.1
(1)
Normal read/write operation is used for all bus access when page read/write access is disabled
(PRENB = 0, PWENB = 0). Even when page read/write access is enabled (PRENB = 1, PWENB
= 1), normal read/write operation is employed in cases where page access cannot be used. Figure
9.2 shows the basic operation of the external bus control signals in read operation, and figure 9.3
shows the basic operation of these signals in write operation.
Rev. 2.00 Sep. 07, 2007 Page 242 of 1312
REJ09B0320-0200
Bit
3 to 0
CKIO
A27 to A0
CSn
RD
WR
D31 to D0
Normal Access
Operation
CSC Interface
Bit Name
ACOSW[3:0] 0000
Ts
Figure 9.2 Basic Bus Timing (Read Operation)
Initial
Value
Tw1 Tw2
CS assert wait
RD assert wait
Read cycle wait
R/W
R/W
Description
AC Characteristics Switch
These bits specify AC characteristics switching.
0000: Does not extend the delay time
0011: Switches characteristics and extends the delay
Other than above: Setting prohibited
time
Twn
Tend
(Trd)
Tn1 Tn2
cycle during read
CS delay
Tnm
Start enable point
of next bus access