R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 919

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

(b) Acknowledge bit at the End of the Control Field
The acknowledge bit at the end of the control field becomes NAK in the following cases and
transfer is stopped.
• When the parity of the control bits is incorrect
• When the bit 3 of the control bits is 1 (data write) although the slave receive buffer* is not
• When the control bits are set to data read (H'3, H'7) although the slave transmit buffer* is
• When another unit which locked the slave unit requests H'3, H'6, H'7, H'A, H'B, H'E, or H'F in
• When the control bits are the locked address read (H'4, H'5) although the unit is not locked
• When a timing error occurs
• When the control bits are undefined
Note: See section 20.1.3 (1), Slave Status Read (Control Bits: H'0, H'6).
(c)
The acknowledge bit at the end of the message length field becomes NAK in the following cases
and transfer is stopped.
• When the parity of the message length bits is incorrect
• When a timing error occurs
(d) Acknowledge Bit at the End of the Data Field
The acknowledge bit at the end of the data field becomes NAK in the following cases and transfer
is stopped.
• When the parity of the data bits is incorrect*
• When a timing error occurs after the previous transfer of the acknowledge bit
• When the receive buffer becomes full and cannot accept further data*
Note: * In this case, the data field is transferred repeatedly until the number of data reaches the
empty
empty
the control bits although the slave unit has been locked
Acknowledge Bit at the End of the Message Length Field
maximum number of transfer bytes if the number of data does not exceed the
maximum number of transfer bytes in one frame.
Section 20 IEBus
Rev. 2.00 Sep. 07, 2007 Page 887 of 1312
TM
Controller (IEB) [R5S72612] [R5S72613]
REJ09B0320-0200