R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 867

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

• Requirements of Bit Configuration Register
SYNC_SEG:
edge transitions occur in this segment.)
PRSEG:
PHSEG1:
PHSEG2:
TSEG1:
TSEG2:
The RCAN-ET Bit Rate Calculation is:
where BRP is given by the register value and TSEG1 and TSEG2 are derived values from TSG1
and TSG2 register values.
BCR Setting Constraints
Bit Rate =
f
TSEG1min > TSEG2 ≥ SJWmax
8 ≤ TSEG1 + TSEG2 + 1 ≤ 25 time quanta (TSEG1 + TSEG2 + 1 = 7 is not allowed)
TSEG2 ≥ 2
CLK
= Peripheral Clock
Segment for compensating for physical delay between networks.
Buffer segment for correcting phase drift (positive). (This segment is extended
when synchronisation (resynchronisation) is established.)
Buffer segment for correcting phase drift (negative). (This segment is shortened
when synchronisation (resynchronisation) is established)
TSG1 + 1
TSG2 + 1
Segment for establishing synchronisation of nodes on the CAN bus. (Normal bit
SYNC_SEG
2 × (BRP + 1) × (TSEG1 + TSEG2 + 1)
1
Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
1-bit time (8 to 25 quanta)
PRSEG
f
clk
TSEG1
4-16
(SJW = 1 to 4)
PHSEG1
Rev. 2.00 Sep. 07, 2007 Page 835 of 1312
TSEG2
2-8
Quantum
REJ09B0320-0200