R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 878

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
19.5.1
The concatenation of TXPR0 and TXPR1 is a 32-bit register that contains any transmit pending
flags for the CAN module. In the case of 16-bit bus interface, Long Word access is carried out as
two consecutive word accesses.
<Longword Write Operation>
Rev. 2.00 Sep. 07, 2007 Page 846 of 1312
REJ09B0320-0200
Description
Mailbox Interrupt Mask Register 0
Unread Message Status Register 0 H'05A
Transmit Pending Register (TXPR0, TXPR1)
Data is stored into Temp instead of TXPR1.
TXPR1
Temp
H'020
16-bit peripheral bus
<Upper word write>
TXPR0
H'022
Address
H'052
H'054
H'056
H'058
H'05C
H'05E
Consecutive access
Name
MBIMR0
UMSR0
Lower word data is stored into TXPR0.
TXPR1
Temp
H'020
TXPR1 is always H'0000.
16-bit peripheral bus
<Lower word write>
Access Size (bits)
Word
Word
TXPR0
H'022