R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 200

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 User Break Controller (UBC)
7.3.1
BAR is a 32-bit readable/writable register. BAR specifies the address used as a break condition in
each channel. The control bits CD[1:0] in the break bus cycle register (BBR) select one of the
three address buses for a break condition. BAR is initialized to H'00000000 by a power-on reset or
in deep standby, but retains its previous value by a manual reset or in software standby mode or
sleep mode.
Note: When setting the instruction fetch cycle as a break condition, clear the LSB in BAR to 0.
Rev. 2.00 Sep. 07, 2007 Page 168 of 1312
REJ09B0320-0200
Bit
31 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Break Address Register (BAR)
BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16
BA15 BA14 BA13 BA12 BA11 BA10 BA9
Bit Name
BA31 to BA0 All 0
R/W
R/W
31
15
0
0
R/W
R/W
30
14
0
0
R/W
R/W
29
13
0
0
Initial
Value
R/W
R/W
28
12
0
0
R/W
R/W
27
11
0
0
R/W
R/W
R/W
R/W
26
10
0
0
Description
Break Address
Store an address on the CPU address bus (FAB or
MAB) or IAB specifying break conditions.
When the C bus and instruction fetch cycle are
selected by BBR, specify an FAB address in bits BA31
to BA0.
When the C bus and data access cycle are selected by
BBR, specify an MAB address in bits BA31 to BA0.
R/W
R/W
25
0
9
0
R/W
R/W
BA8
24
0
8
0
R/W
R/W
BA7
23
0
7
0
R/W
R/W
BA6
22
0
6
0
R/W
R/W
BA5
21
0
5
0
R/W
R/W
BA4
20
0
4
0
R/W
R/W
BA3
19
0
3
0
R/W
R/W
BA2
18
0
2
0
R/W
R/W
BA1
17
0
1
0
R/W
R/W
BA0
16
0
0
0