R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 958

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 20 IEBus
20.3.21 IEBus Transmit Data Buffer 001 to 128 (IETB001 to IETB128)
IETB001 to IETB128 are 128-byte (8 × 128) buffers to which data to be transmitted during master
transmission is written.
IETB001 to IETB128 are initialized by a power-on reset or in deep standby. The initial values are
undefined.
Note:
Rev. 2.00 Sep. 07, 2007 Page 926 of 1312
REJ09B0320-0200
Bit
7 to 0
*
Bit Name
TBn
Writing to these bits during master transmission (MRQ in IEFLG is 1) is prohibited.
TM
Controller (IEB) [R5S72612] [R5S72613]
Initial value:
Initial
Value
Undefined W*
[Legend]
n = 0011 to 128
R/W:
Bit:
—
7
W*
R/W
—
6
W*
Description
IEBus Transmit Data Buffer
Data to be transmitted in the data field during master
transmission is written to TB001 to TB128.
Data is written starting with TB001 for the start 1-byte
data, followed by TB002 and TB003 and so on
according to the transmission order, and TB128 stores
the last data.
W*
—
5
W*
—
4
TBn
W*
—
3
W*
—
2
W*
—
1
W*
—
0
W*