R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 795

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

No
No
No
Clear ACKBT in ICIER to 0
Clear RCVD in ICCR1 to 0
Write 0 to BBSY and SCP
Set ACKBT in ICIER to 1
Clear MST in ICCR1 to 0
Clear TRS in ICCR1 to 0
Set RCVD in ICCR1 to 1
Master receive mode
Dummy-read ICDRR
Read RDRF in ICSR
Read RDRF in ICSR
Clear TEND in ICSR
Clear TDRE in ICSR
Clear STOP in ICSR
Read STOP in ICSR
Read ICDRR
Read ICDRR
Read ICDRR
Last receive
RDRF = 1 ?
STOP = 1 ?
RDRF=1 ?
Figure 17.19 Sample Flowchart for Master Receive Mode
- 1?
End
Yes
Yes
Yes
No
Yes
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[1] Clear TEND, select master receive mode,
[2] Set acknowledge to the transmit device. *
[3] Dummy-read ICDDR. *
[4] Wait for 1 byte to be received
[5] Check whether it is the (last receive - 1).
[6] Read the receive data.
[7] Set acknowledge of the final byte.
[8] Read the (final byte - 1) of received data.
[9] Wait for the last byte to be receive.
[10] Clear the STOP flag.
[11] Issue the stop condition.
[12] Wait for the creation of stop condition.
[13] Read the last byte of receive data.
[14] Clear RCVD.
[15] Set slave receive mode.
Notes: * Make sure that no interrupt will be generated during
and then clear TDRE. *
Disable continuous reception (RCVD = 1).
steps [1] to [3].
When the size of receive data is only one byte in
reception, steps [2] to [6] are skipped after step [1],
before jumping to step [7].
The step [8] is dummy-read in ICDRR.
Rev. 2.00 Sep. 07, 2007 Page 763 of 1312
Section 17 I
2
C Bus Interface 3 (IIC3)
REJ09B0320-0200