R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 129

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

5.1.2
The exception handling sources are detected and begin processing according to the timing shown
in table 5.2.
Table 5.2
Exception
Reset
Address error
Bus error
Interrupts
Register bank
error
Instructions
Exception Handling Operations
Timing of Exception Source Detection and Start of Exception Handling
Source
Power-on reset
Manual reset
Bank underflow
Bank overflow
Trap instruction
General illegal
instructions
Slot illegal
instructions
Integer division
instructions
Floating-point
operation
instruction
Timing of Source Detection and Start of Handling
Starts when the RES pin changes from low to high, when the
H-UDI reset negate command is set after the H-UDI reset
assert command has been set, or when the WDT overflows.
Starts when the MRES pin changes from low to high or when
the WDT overflows.
Detected when instruction is decoded and starts when the
previous executing instruction finishes executing.
Starts upon attempted execution of a RESBANK instruction
when saving has not been performed to register banks.
In the state where saving has been performed to all register
bank areas, starts when acceptance of register bank overflow
exception has been set by the interrupt controller (the BOVE bit
in IBNR of the INTC is 1) and an interrupt that uses a register
bank has occurred and been accepted by the CPU.
Starts from the execution of a TRAPA instruction.
Starts from the decoding of undefined code anytime except
immediately after a delayed branch instruction (delay slot).
Starts from the decoding of undefined code placed immediately
after a delayed branch instruction (delay slot), of instructions
that rewrite the PC, of 32-bit instructions, of the RESBANK
instruction, of the DIVS instruction, or of the DIVU instruction.
Starts when detecting division-by-zero exception or overflow
exception caused by division of the negative maximum value
(H'80000000) by −1.
Exception handling starts triggered by disabled operation
exception of floating-point operation instruction (IEEE754
standard), division exception by zero, overflow, underflow, or
imprecise exception. Setting the QIS bit in FPSCR or inputting
qNaN as well as ±∞ as the floating-point operation instruction
source also starts exception handling.
Rev. 2.00 Sep. 07, 2007 Page 97 of 1312
Section 5 Exception Handling
REJ09B0320-0200