R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 590

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.7.9
If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will
be the data in the buffer before input capture transfer for channels 0 to 4, and the data after input
capture transfer for channel 5.
Figures 12.114 and 12.115 show the timing in this case.
Rev. 2.00 Sep. 07, 2007 Page 558 of 1312
REJ09B0320-0200
Figure 12.114 Contention between TGR Read and Input Capture (Channels 0 to 4)
Figure 12.115 Contention between TGR Read and Input Capture (Channel 5)
Contention between TGR Read and Input Capture
Pφ
Address
Read signal
Input capture
signal
TGR
Internal data
bus
Pφ
Address
Read signal
Input capture
signal
TGR
Internal data
bus
N
N
TGR read cycle
TGR read cycle
T1
T1
TGR address
TGR address
T2
T2
M
N
M
M