R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 798

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R5S72611

Manufacturer Part Number
R5S72611
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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Section 17 I
17.5
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,
NACK detection, STOP recognition, and arbitration lost/overrun error. Table 17.4 shows the
contents of each interrupt request.
Table 17.4 Interrupt Requests
When the interrupt condition described in table 17.4 is 1, the CPU executes an interrupt exception
handling. Note that a TXI or RXI interrupt can activate the DMAC if the setting for DMAC
activation has been made. In such a case, an interrupt request is not sent to the CPU. Interrupt
sources should be cleared in the exception handling. The TDRE and TEND bits are automatically
cleared to 0 by writing the transmit data to ICDRT. The RDRF bit is automatically cleared to 0 by
reading ICDRR. The TDRE bit is set to 1 again at the same time when the transmit data is written
to ICDRT. Therefore, when the TDRE bit is cleared to 0, then an excessive data of one byte may
be transmitted.
Rev. 2.00 Sep. 07, 2007 Page 766 of 1312
REJ09B0320-0200
Interrupt Request
Transmit data Empty
Transmit end
Receive data full
STOP recognition
NACK detection
Arbitration lost/
overrun error
Interrupt Requests
2
C Bus Interface 3 (IIC3)
Abbreviation
TXI
TEI
RXI
STPI
NAKI
Interrupt Condition
(TDRE = 1) • (TIE = 1)
(TEND = 1) • (TEIE = 1)
(RDRF = 1) • (RIE = 1)
(STOP = 1) • (STIE = 1)
{(NACKF = 1) + (AL = 1)} •
(NAKIE = 1)
I
Format
2
C Bus
Clocked Synchronous
Serial Format

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