R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 185

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

6.7
Table 6.5 lists the interrupt response time, which is the time from the occurrence of an interrupt
request until the interrupt exception handling starts and fetching of the first instruction in the
interrupt exception service routine begins. The interrupt processing operations differ in the cases
when banking is disabled, when banking is enabled without register bank overflow, and when
banking is enabled with register bank overflow. Figures 6.4 and 6.5 show examples of pipeline
operation when banking is disabled. Figures 6.6 and 6.7 show examples of pipeline operation
when banking is enabled without register bank overflow. Figures 6.8 and 6.9 show examples of
pipeline operation when banking is enabled with register bank overflow.
Table 6.5
Item
Time from occurrence of
interrupt request until interrupt
controller identifies priority,
compares it with mask bits in
SR, and sends interrupt request
signal to CPU
Time from
input of
interrupt
request
signal to
CPU until
sequence
currently
being
executed is
completed,
interrupt
exception
handling
starts, and
first
instruction in
interrupt
exception
service
routine is
fetched
Interrupt Response Time
No
register
banking
Register
banking
without
register
bank
overflow
Register
banking
with
register
bank
overflow
Interrupt Response Time
Min.
Max. 4 Icyc + 2 (m1 + m2) + m3
Min.
Max. 
Min.
Max. 
NMI
2 Icyc +
2 Bcyc +
1 Pcyc
3 Icyc + m1 + m2


User Break H-UDI
3 Icyc
Number of States
2 Icyc +
1 Pcyc
3 Icyc + m1 + m2
12 Icyc + m1 + m2
3 Icyc + m1 + m2
3 Icyc + m1 + m2 + 19 (m4)
IRQ, PINT
2 Icyc +
3 Bcyc +
1 Pcyc
Rev. 2.00 Sep. 07, 2007 Page 153 of 1312
Section 6 Interrupt Controller (INTC)
Peripheral
Module
2 Icyc +
1 Bcyc +
1 Pcyc
Remarks
Min. is when the interrupt
wait time is zero.
Max. is when a higher-
priority interrupt request
has occurred during
interrupt exception
handling.
Min. is when the interrupt
wait time is zero.
Max. is when an interrupt
request has occurred
during execution of the
RESBANK instruction.
Min. is when the interrupt
wait time is zero.
Max. is when an interrupt
request has occurred
during execution of the
RESBANK instruction.
REJ09B0320-0200