R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 782

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 17 I
Rev. 2.00 Sep. 07, 2007 Page 750 of 1312
REJ09B0320-0200
(Master output)
(Master output)
(Slave output)
(Master output)
(Master output)
processing
(Slave output)
ICDRS
ICDRT
TDRE
TEND
processing
User
SDA
SDA
SCL
ICDRS
ICDRT
SCL
SDA
SDA
TDRE
TEND
User
[2] Instruction of start
2
C Bus Interface 3 (IIC3)
condition issuance
[5] Write data to ICDRT
Figure 17.5 Master Transmit Mode Operation Timing (1)
Figure 17.6 Master Transmit Mode Operation Timing (2)
9
A
Bit 7
1
Bit 7
[3] Write data to ICDRT (first byte)
1
Bit 6
2
Bit 6
2
Address + R/W
Bit 5
3
Address + R/W
Slave address
Bit 5
3
Data n
Bit 4
4
Data n
Bit 4
4
Bit 3
5
Bit 3
5
Bit 2
6
[4] Write data to ICDRT (second byte)
Bit 2
6
Bit 1
7
[6] Issue stop condition. Clear TEND.
Bit 1
7
R/W
Bit 0
8
Bit 0
8
[5] Write data to ICDRT (third byte)
A
9
[7] Set slave receive mode
A/A
9
Data 1
Data 1
Bit 7
1
Bit 6
Data 2
2