R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 445

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

12.3.5
The TIER registers are 8-bit readable/writable registers that control enabling or disabling of
interrupt requests for each channel. The MTU2 has seven TIER registers, two for channel 0 and
one each for channels 1 to 5.
• TIER_0, TIER_1, TIER_2, TIER_3, TIER_4
Bit
0
Bit
7
Bit Name
CMPCLR5W 0
Bit Name
TTGE
Timer Interrupt Enable Register (TIER)
Initial value:
Initial
Value
Initial
Value
0
R/W:
Bit:
TTGE TTGE2 TCIEU TCIEV TGIED TGIEC TGIEB TGIEA
R/W
R/W
R/W
R/W
R/W
7
0
R/W
6
0
Description
TCNT Compare Clear 5W
Enables or disables requests to clear TCNTW_5 at
TGRW_5 compare match or input capture.
0: Disables TCNTW_5 to be cleared to H'0000 at
1: Enables TCNTW_5 to be cleared to H'0000 at
Description
A/D Converter Start Request Enable
Enables or disables generation of A/D converter start
requests by TGRA input capture/compare match.
0: A/D converter start request generation disabled
1: A/D converter start request generation enabled
R/W
5
0
TCNTW_5 and TGRW_5 compare match or input
capture
TCNTW_5 and TGRW_5 compare match or input
capture
R/W
4
0
Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
R/W
3
0
Rev. 2.00 Sep. 07, 2007 Page 413 of 1312
R/W
2
0
R/W
1
0
R/W
0
0
REJ09B0320-0200