R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 507

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R5S72611

Manufacturer Part Number
R5S72611
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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(3)
I2AE bit in TICCR has been set to 1 to include the TIOC2A pin in the TGRA_1 input capture
conditions. In this example, the IOA0 to IOA3 bits in TIOR_1 have selected the TIOC1A rising
edge for the input capture timing while the IOA0 to IOA3 bits in TIOR_2 have selected the
TIOC2A rising edge for the input capture timing.
Under these conditions, the rising edge of both TIOC1A and TIOC2A is used for the TGRA_1
input capture condition. For the TGRA_2 input capture condition, the TIOC2A rising edge is used.
Figure 12.22 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the
TGRA_1
TGRA_2
TCNT_1
TIOC1A
TIOC2A
H'FFFF
H'C256
H'6128
H'0000
Cascaded Operation Example (b)
TCNT_2 value
Figure 12.22 Cascaded Operation Example (b)
H'0512
As I1AE in TICCR is 0, data is not captured in TGRA_2 at the TIOC1A input timing.
H'0512
H'0513
Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Rev. 2.00 Sep. 07, 2007 Page 475 of 1312
H'0514
H'C256
H'0513
REJ09B0320-0200
Time

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