R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 785

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

17.4.4
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs
the receive clock and returns an acknowledge signal. For slave transmit mode operation timing,
refer to figures 17.9 and 17.10.
The transmission procedure and operations in slave transmit mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set bits CKS[3:0] in ICCR1. (Initial setting) Set the MST and
2. When the slave address matches in the first frame following detection of the start condition,
3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1,
4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is opened.
5. Clear TDRE.
(Master output)
(Master output)
(Slave output)
processing
TRS bits in ICCR1 to select slave receive mode, and wait until the slave address matches.
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS bit in ICCR1 and the TDRE bit
in ICSR are set to 1, and the mode changes to slave transmit mode automatically. The
continuous transmission is performed by writing transmit data to ICDRT every time TDRE is
set.
with TDRE = 1. When TEND is set, clear TEND.
ICDRS
ICDRR
SCL
SDA
SDA
RCVD
RDRF
User
Slave Transmit Operation
Data n-1
Figure 17.8 Master Receive Mode Operation Timing (2)
A
9
[5] Read ICDRR after setting RCVD
Data n-1
Bit 7
1
Bit 6
2
Bit 5
3
Bit 4
4
Bit 3
5
[6] Issue stop
condition
Bit 2
6
Rev. 2.00 Sep. 07, 2007 Page 753 of 1312
Bit 1
7
Section 17 I
[7] Read ICDRR,
Bit 0
Data n
8
and clear RCVD
A/A
9
2
C Bus Interface 3 (IIC3)
Data n
REJ09B0320-0200
[8] Set slave
receive mode