R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 352
R5S72611
Manufacturer Part Number
R5S72611
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5S72611.pdf
(1348 pages)
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Section 11 Direct Memory Access Controller (DMAC)
Rev. 2.00 Sep. 07, 2007 Page 320 of 1312
REJ09B0320-0200
Bit
23 to 19
18 to 16 SZSEL[2:0] Undefined R/W
15
14 to 12 SAMOD
11
Bit Name
[2:0]
Initial
Value
All 0
0
Undefined R/W
0
R/W
R
R
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Transfer Data Size Selection
These bits are used to specify the number of bits
transferred in each single data transfer. The unit for
transfer can be selected as byte (8 bit), word (16 bit),
or longword (32 bit). For details, see section 11.9,
Units of Transfer and Positioning of Bytes for Transfer.
Set the transfer size so that it doesn't exceed the
widths of the data buses supported by the source and
destination for DMA transfer. The bus widths of the
data buses are fixed by hardware.
000: Byte (8 bits)
001: Word (16 bits)
010: Longword (32 bits)
011 to 111: Setting prohibited
Reserved
This bit is always read as 0. The write value should
always be 0.
Source Address Direction Control
These bits are used to specify the direction of counting
for the source address.
000: Fixed
001: Incrementation
010: Decrementation
011: Rotation
100 to 111: Setting prohibited
Reserved
This bit is always read as 0. The write value should
always be 0.
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