R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 991

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Note: The setting of this register is reapplied on each sector-to-sector transition.
21.3.7
CROMCTL5 specifies the representation mode for HEAD20 to HEAD22.
Bit
4
3
2 to 0
Bit
7 to 1
0
Bit Name
ER0SEL
NO_ECC

Bit Name

MSF_LBA_
SEL
HEAD20 to HEAD22 Representation Control Register (CROMCTL5)
Initial value:
Initial
Value
0
0
All 0
Initial
Value
All 0
0
R/W:
Bit:
R/W
—
7
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
6
0
Description
CD-ROM Data-Related Status Register Setting
Condition
0: Information is on the sector being decoded.
1: Information is on the latest sector that has been
This condition affects the information given by bits 5 to
0 in the CROMST0 register, bits 7 to 1 in the
CROMST4 and CROMST5 registers, and HEAD00 to
HEAD02.
ECC correction mode when the result of the EDC check
before ECC correction was 'pass'
When this bit is set to 1, ECC correction is not
performed if the result of pre-correction EDC checking
is a 'pass', regardless of the results of syndrome
calculation.
Reserved
These bits are always read as 0. The write value should
always be 0.
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
HEAD20 to HEAD22 Representation Mode
0: BCD M, F, and S values in the header as is
1: Total sector number in HEX
R/W
—
5
0
buffered.
R/W
—
4
0
R/W
—
3
0
Section 21 CD-ROM Decoder (ROM-DEC)
Rev. 2.00 Sep. 07, 2007 Page 959 of 1312
R/W
—
2
0
R/W
—
1
0
LBA_SEL
R/W
MSF_
0
0
REJ09B0320-0200