R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 977

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

21.2
Figure 21.2 is a block diagram of the CD-ROM decoder functions of this LSI and the bus bridge
for connection to the peripheral bus, that is, of the elements required to implement the CD-ROM
decoder function.
The core of the CD-ROM decoder executes a series of processing required for CD-ROM
decoding, including descrambling, sync code detection, ECC correction (P- and Q-parity-based
correction), and EDC checking. The core includes sufficient memory to hold two sectors.
Stream data
Block Diagrams
Descrambler
maintenance
Sync code
generation
detection/
Timing
Figure 21.2 ROM-DEC Block Diagram
Bus bridge (peripheral bus ⇔ ROM-DEC bus)
INTC interrupt and DMAC activation control
determination
Peripheral bus controller
Syndrome
calculator
EDC
Mode
SH-2A CPU
INTC DMAC
Register data
(2 buffers for ECC)
ECC control
Memory
Memory
control
Section 21 CD-ROM Decoder (ROM-DEC)
Rev. 2.00 Sep. 07, 2007 Page 945 of 1312
Core of CD-ROM decoder
EDC
Stream data
REJ09B0320-0200