R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 21

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

16.4 Operation ........................................................................................................................... 706
16.5 SCIF Interrupts .................................................................................................................. 725
16.6 Usage Notes ....................................................................................................................... 726
Section 17 I
17.1 Features.............................................................................................................................. 729
17.2 Input/Output Pins ............................................................................................................... 731
17.3 Register Descriptions ......................................................................................................... 732
17.4 Operation ........................................................................................................................... 748
17.5 Interrupt Requests .............................................................................................................. 766
16.3.10 FIFO Data Count Register (SCFDR) .................................................................... 702
16.3.11 Serial Port Register (SCSPTR) ............................................................................. 703
16.3.12 Line Status Register (SCLSR) .............................................................................. 705
16.4.1 Overview............................................................................................................... 706
16.4.2 Operation in Asynchronous Mode ........................................................................ 708
16.4.3 Operation in Clocked Synchronous Mode ............................................................ 717
16.6.1 SCFTDR Writing and TDFE Flag ........................................................................ 726
16.6.2 SCFRDR Reading and RDF Flag ......................................................................... 726
16.6.3 Restriction on DMAC Usage ................................................................................ 727
16.6.4 Break Detection and Processing ........................................................................... 727
16.6.5 Sending a Break Signal......................................................................................... 727
16.6.6 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode) ...... 728
17.3.1 I
17.3.2 I
17.3.3 I
17.3.4 I
17.3.5 I
17.3.6 Slave Address Register (SAR).............................................................................. 745
17.3.7 I
17.3.8 I
17.3.9 I
17.3.10 NF2CYC Register (NF2CYC) .............................................................................. 747
17.4.1 I
17.4.2 Master Transmit Operation ................................................................................... 749
17.4.3 Master Receive Operation..................................................................................... 751
17.4.4 Slave Transmit Operation ..................................................................................... 753
17.4.5 Slave Receive Operation....................................................................................... 756
17.4.6 Clocked Synchronous Serial Format..................................................................... 757
17.4.7 Noise Filter ........................................................................................................... 761
17.4.8 Example of Use..................................................................................................... 762
2
2
2
2
2
2
2
2
2
2
C Bus Control Register 1 (ICCR1)..................................................................... 733
C Bus Control Register 2 (ICCR2)..................................................................... 736
C Bus Mode Register (ICMR)............................................................................ 738
C Bus Interrupt Enable Register (ICIER) ........................................................... 740
C Bus Status Register (ICSR)............................................................................. 742
C Bus Transmit Data Register (ICDRT)............................................................. 746
C Bus Receive Data Register (ICDRR).............................................................. 746
C Bus Shift Register (ICDRS)............................................................................ 746
C Bus Format...................................................................................................... 748
C Bus Interface 3 (IIC3) ................................................................729
Rev. 2.00 Sep. 07, 2007 Page xxi of xxxii