PM7311 pmc-sierra, PM7311 Datasheet - Page 95

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
10.9.17
10.9.18
10.9.19
Digital Delay Lock Loop (DDLL)
The DLL is used to minimize output delay on all external RAMs. The DLL measures the phase
difference between the external clock and a reference clock and generates an internal clock,
which reduces the phase difference between the external clock and the reference clock to zero.
JTAG Test Access Port
The JTAG Test Access Port block provides JTAG support for boundary scan. The standard JTAG
EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported. The
FREEDM 84A1024L identification code is 073100CD hexadecimal.
Microprocessor Interface
The FREEDM 84A1024L supports microprocessor access to an internal register space for
configuring and monitoring the device. All registers are on 32 bit boundaries. Address Bit 12 on
all registers must be set to 0. The registers are described in Table 13.
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Released
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