PM7311 pmc-sierra, PM7311 Datasheet - Page 120

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
Register 0x068: DLL Configuration
The DLL Configuration Register controls the basic operation of the DLL.
LOCK
VERN_EN
ERRORE
Reserved
The LOCK register is used to force the DLL to ignore phase offsets indicated by the phase
detector after phase lock has been achieved. When LOCK is set to logic zero, the DLL will
track phase offsets measured by the phase detector between the DLLSYSCLK and the
DLLREFCLK inputs. When LOCK is set to logic one, the DLL will not change the tap after
the phase detector indicates a zero phase offset between the DLLSYSCLK and the
DLLREFCLK inputs for the first time.
The vernier enable register (VERN_EN) forces the DLL to ignore the phase detector and use
the tap number specified by the VERNIER[7:0] register bits. When VERN_EN is set to logic
zero, the DLL operates normally adjusting the phase offset based on the phase detector.
When VERN_EN is set to logic one, the delay line uses the tap specified by the
VERNIER[7:0] register bits.
The ERROR interrupt enable (ERRORE) bit enables the error indication interrupt. When
ERRORE is set high, an interrupt is generated upon assertion event of the ERR output and
ERROR register. When ERRORE is set low, changes in the ERROR and ERR status do not
generate an interrupt.
The reserved bits must be set low for correct operation of the FREEDM 84A1024L device.
Bit
Bit 31
To
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Function
Unused
Reserved
Reserved
Unused
ERRORE
VERN_EN
LOCK
Default
X
0
0
X
X
0
0
Released
120