PM7311 pmc-sierra, PM7311 Datasheet - Page 138

• Manufacturer Part Number: PM7311
• Description: Freedm 84a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021832, Issue 2
CRC[1:0]
INVERT
PRIORITY
7BIT
The CRC algorithm bits (CRC[1:0]) configures the HDLC processor to perform CRC
verification on the incoming data stream. The value of CRC[1:0] to be written to the channel
provision RAM, in an indirect channel write operation, must be set up in this register before
triggering the write. CRC[1:0] reflects the value written until the completion of a subsequent
indirect channel read operation.
Table 18 CRC[1:0] Settings
The HDLC data inversion bit (INVERT) configures the HDLC processor to logically invert
the incoming HDLC stream from the RCAS-12 before processing it. The value of INVERT
to be written to the channel provision RAM, in an indirect channel write operation, must be
set up in this register before triggering the write. When INVERT is set to one, the HDLC
stream is logically inverted before processing. When INVERT is set to zero, the HDLC
stream is not inverted before processing. INVERT reflects the value written until the
completion of a subsequent indirect channel read operation. Before tearing down a channel,
this bit must be set to 0.
The channel FIFO priority bit (PRIORITY) informs the partial packet processor that the
channel has precedence over other channels when being serviced by upstream blocks. The
value of PRIORITY to be written to the channel provision RAM, in an indirect channel write
operation, must be set up in this register before triggering the write. Channel FIFOs with
PRIORITY set to one are serviced before channel FIFOs with PRIORITY set to zero.
Channels with an HDLC data rate to FIFO size ratio that is significantly higher than other
channels should have PRIORITY set to one. PRIORITY reflects the value written until the
completion of a subsequent indirect channel read operation.
The 7BIT enable bit (7BIT) configures the HDLC processor to ignore the least significant bit
of each octet in the incoming channel stream. The value of 7BIT to be written to the channel
provision RAM, in an indirect channel write operation, must be set up in this register before
triggering the write. When 7BIT is set high, the least significant bit (last bit of each octet
received), is ignored. When 7BIT is set low, the entire receive data stream is processed.
7BIT reflects the value written until the completion of a subsequent indirect channel read
operation.
CRC[1]
0
0
1
1
CRC[0]
0
1
0
1
Operation
No Verification
CRC-CCITT
CRC-32
Reserved
FREEDM 84A1024L ASSP Telecom Standard Product Data Sheet
Released
138